Demonstration videos


Name Products Type Action

635 results (page 1/32)

01 ALINT-PRO Installation    Learn how to install and run ALINT-PRO

ALINT-PRO Tutorials

01-Creating HDL Text Modules    Learn how to create HDL Text Modules in Active-HDL

Active-HDL Tutorials

02 ALINT-PRO Workspace and Projects    Learn how to work with the design structure in ALINT-PRO

ALINT-PRO Tutorials

02-Creating HDL Graphical Modules    Learn how to create schematic diagram and finite state machine in Active-HDL

Active-HDL Tutorials

03 ALINT-PRO Design Analysis    Learn how to run design analysis with ALINT-PRO

ALINT-PRO Tutorials

03-Design Flow Manager    Learn how to use Design Flow Manager in Active-HDL

Active-HDL Tutorials

04 ALINT-PRO Results Analysis    Learn how to analyze linting results with ALINT-PRO

ALINT-PRO Tutorials

04-Creating Testbenches    Learn how to create a Testbench in Active-HDL

Active-HDL Tutorials

05 ALINT-PRO RTL Schematic    Learn how to use the RTL Schematic Viewer in ALINT-PRO

ALINT-PRO Tutorials

05-Running Simulation    Learn how to run simulation and use waveform viewer in Active-HDL

Active-HDL Tutorials

06 ALINT-PRO Command-line and Batch Mode    Learn how to use ALINT-PRO in batch mode

ALINT-PRO Tutorials

06-HDL_Debugging    Learn how to use HDL debugging tools in Active-HDL

Active-HDL Tutorials

07 ALINT-PRO Unit Linting with Active-HDL    Learn how to run unit linting with ALINT-PRO

ALINT-PRO Tutorials

07-Code_Coverage    Learn how to use Code Coverage in Active-HDL

Active-HDL Tutorials

08 ALINT-PRO Unit Linting with Riviera-PRO    Learn how to run ALINT-PRO unit linting within Riviera-PRO framework

ALINT-PRO Tutorials

08-Design_Profiler    Learn how to use Design Profiler

Active-HDL Tutorials

09-Documentation_Features    Learn how to export designs to HTML and PDF in Active-HDL

Active-HDL Tutorials

10-Simulink Interface    Learn how to use Simulink Interface in Active-HDL

Active-HDL Tutorials

7-Series FPGA Chips Programming on the HES7XV690-4000BP Board   

HES-7 Application Notes

Accelerate SoC Simulation Time of Newer Generation FPGAs    Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.

HES-DVM White Papers

Selecting format

If your edition of Active-HDL is equipped with accelerated waveform, it is selected as the default following installation. To change it to standard
viewer/editor or back to accelerated viewer, you can use GUI or console commands. Changing format is possible only when simulation is not running.

To change the default waveform format in GUI:

  1. Go to Tools | Preferences

  2. When Preferences window opens, click Waveform Viewer/Editor entry in the Editors section of the Category: box

  3. Pick Standard Waveform Viewer/Editor or Accelerated Waveform Viewer entry from the list in the Default Waveform Viewer/Editor box (see Figure 1)

Figure 1: Default waveform format selection.

To check or change the default waveform format in the console or macro, use the waveformmode command with the following syntax:

  • waveformmode without arguments displays current default setting

  • waveformmode asdb sets default format to accelerated waveform viewer

  • waveformmode awf sets default format to standard viewer/editor

Simulation Macros

Macros Entered in the Console Window

Active-HDL provides a macro command language for manually entering simulation commands,
such as forcing signal values, assigning formulas and executing simulation steps. You can force a value on
a signal at any time during simulation by entering the appropriate macro commands in the Console window.
You can also use macro commands to add forced signals to the Waveform Editor, etc.

Figure 3. The Console window


  • Wave — creates an empty waveform

  • Wave CE — adds CE signal to waveform

  • Wave RESET — adds RESET signal to waveform

  • Wave LOAD — adds LOAD signal to waveform

  • Wave DIN — adds DIN signal to waveform

  • Wave DIR — adds DIR signal to waveform

  • Force LOAD 1 0ns, 0 10ns — changes LOAD to 1 at 0ns and to 0 at 10ns

  • Force CE 1 — changes CE to 1

Files Containing Macros

The simulation macro commands can be executed from a file, saving you time on the manual entry of
every command in the Console window. Simulation macros not only can force input signals but they
can also execute other commands in the Active-HDL environment. This allows complete automation of the
design verification process, particularly when combined with other simulation entry methods. For example,
you can write a script to run a number of simulations using several TestBench files, one after another.
Macro scripts can execute external programs such as a synthesis program, batch files, etc. You can also
invoke custom commands developed in Script Basic, which are included with Active-HDL, for automation purposes.

Advantages of Macro commands

  • Fast stimulator entry, directly from keyboard.

  • No need to use GUI windows.

  • Familiar to Model Technology simulator users.

  • Allows automation of the entire simulation process.

Disadvantages of Macro Commands

  • Proprietary format of the simulation commands.

  • Requires knowledge of the macro language commands.

Figure 4. The Macro Command File

VHDL TestBench in IEEE WAVES Format

The TestBench wizard allows you to create a template compliant with the IEEE WAVES 1029.1 specification. WAVES is a
specification for creating TestBench files in the VHDL language. It describes simulation inputs with a specific language
implemented as a set of VHDL libraries. It supports verification and testing of hardware designs at any level of abstraction.
You do not have to be familiar with the WAVES specification to create these files. If you select this option, the
TestBench Wizard will automatically format your TestBench program using the WAVES specification. The main benefit
of using this format is the ability to format simulation input and output files so that they can be used interchangeably
between various simulators. The WAVES format also contains some very useful high level functions for comparing simulation
outputs without writing a lot of VHDL code. The standard TestBench functions are provided in a compiled WAVES library and
allow reading and writing of TestBench files in the WAVES format.

The difference between the WAVES TestBench and other TestBench files are:

  • It provides a standard file format for waveform data, including formula expressions and stimulator types

  • It has some very useful high level functions for typical TestBench operations

Call Stack Window

The Call Stack window is a debugging tool that displays a list of subprograms (procedures and functions) and variables being currently executed. The term process is used here to mean any concurrent statement modeling a sequential process in the elaborated model. Such statements are process statements, concurrent signals assignment statements, concurrent assertion statements, and concurrent procedure call statements (exactly the same as for the Processes window). For each subprogram, the window displays the following information:

  • Formal parameters along with their actual values.

  • Variables, constants and files declared locally in subprogram bodies along with their current values.

If there is more than one process in the simulated design, you can use the Processes window to select the process whose subprograms you want to watch. The Call Stack window is available only while the simulator is running.

The Call Stack Window


Several recent releases of Active-HDL were equipped with an optional, stand-alone accelerated waveform viewer, ASDB Waveform. Starting with Active-HDL 7.3,
both regular waveform (.awf format) and accelerated waveform (.awc/.asdb format) are integrated with the GUI, but only one format can be used during a
given simulation session. This document describes how to select the desired format.

Accelerated waveform is preferred when simulation has to run for long period of time, large number of signals must be observed, and waveform editing
capabilities are not required.

NOTE: Not all editions of Active-HDL have accelerated waveform enabled in the license (you can check if you have it enabled by looking for the Accelerated
Waveform Viewer feature status in Help | License Information | Diagnose License).

Code Tracing

When the code syntax is error-free you can start verifying the models behavior. Active-HDL provides you with Waveform Editor, where all results are presented in the form of waveforms. You can quickly find any faulty and undesired design responses.

To get more specific information on the Waveform Editor, please refer to the application note on Waveform Editor features.

Active-HDL provides an interactive graphical environment for design development and verification. When necessary, you can trace the HDL source code statement-by-statement. There are four functions that allow you to trace the code:

  • Trace into — executes a single HDL statement. If a subprogram call is encountered, the execution descends into the subprogram body.

  • Trace over — executes a single VHDL or Verilog command. If a subprogram call is encountered, the statements contained within the subprogram body are executed in a single step.

  • Trace out — executes as many HDL statements as required to complete the execution of a subprogram. If subprograms are nested, the command completes the execution of the innermost subprogram only.

  • Trace over transition — executes as many HDL statements as required to perform a transition between states.

To perform any of these commands, choose the appropriate options from the Simulation menu or click the Trace icons. The last transition option is available only while verifying state machines.


A design is stored in a folder whose name is usually the same as the design name. The content of its subfolders are as follows:

• \compile

Temporary and intermediate file — among others, VHDL, Verilog, and EDIF files generated from block and state diagrams.

• \implement

The files produced by the implementation tool used to process the design.

• \log

Console log files.

• \slp

Contains the slp_model.dll dynamically-linked library and intermediate files generated by SLP; the directory is created when simulation is initialized with SLP acceleration enabled.

• \src

Design source files and other resource files displayed on the Files tab of Design Browser.

• \synthesis

The files produced by the synthesis tool employed to process the design.

• \<design_name>_synthesis

Post-synthesis library files.

• \<design_name>_timing

Timing library files.

Files residing directly in the design folder:

• <design_name>.adf is the design description file.

• <design_name>.aws is the workspace description file.

• Edfmap.ini:- to enable simulation of EDIF netlists generated by different tools, Active-HDL allows remapping of cell names, pin names, and library names appearing in primitive cell instantiations. Such a remapping allows using a reduced set of universal primitive libraries and is performed automatically during compilation of netlist files. The description of the remapping rules resides in the Edfmap.ini.

• compililation.order:- It contains compilation order of files and is also the default synthesis order if the synthesis order (synthesis.order)is not specified.

• <design_name>.wsp stores information on the current layout of the Active-HDL framework window.

• <design_name>.lib and *.mgf files store the default working library of the design.

• compile.cfg, fsm.set, and bde.set are additional block/state diagram configuration files.

To copy a design manually, you must copy the entire design folder. Keep in mind, that designs may include links to files stored outside their design folders.

However we recommend adding everything from src folder and all files under design folder except *.mgf ,*.cfg and *.lib files. You do not need to add anything to compile or log sub folders.

When you run your design, you will need to recompile your design files prior to running simulation.

You can pack and save the current design or the entire workspace with all its designs in a ZIP-format archive file. So created archive file can contain a customized set of items added to the «root» including files and subfolders. Long file names are preserved. To unzip such an archive file, you can use any extracting program that accepts the ZIP format.

To archive the current workspace/design, choose Archive Workspace or Archive Design from the Workspace or Design menu, respectively and follow instructions of Archive Workspace/Design Wizard .

For details on Archive Workspace/Design Wizard dialog boxes, see the Specifying the Archive File Settings, Specifying the Contents of the Archive, and Creating the Archive topics, respectively.

To Run A Timing simulation

To run a timing simulation, switch the design view to Implementation.

Figure 7 Design View: Implementation

  • Run the synthesis and implementation process by pressing the Implement Top Module button or by right-clicking the top-level module and selecting Implement Top Module.

    Figure 8 Run Synthesis and Implementation Process

  • Expand Implement Design and run the Generate Post-Place & Route Simulation Model process.

    Figure 9 Generate Post-Place & Route Simulation Model

  • Switch the design view to Simulation and change the drop down box from Behavioral to Post Route.

    Figure 10 Post Route Simulation

  • Right-click on Simulate Post-Place & Route Model in the processes window and select Process Properties.

  • You can observe the additional field Delay Values To Be Read from SDF, this indicates an SDF was created to run a timing simulation.

    Figure 11 Process Properties for Timing Simulation

  • The Display Properties should remain the same as the previous simulation.

  • Under Simulation Model Properties you can also observe the -sdf switches used for the timing simulation.

    Figure 12 Simulation Model Properties

  • Run the simulation by right-clicking on Simulate Post-Place & Route Model and select run.

Additional Information Setting Environmental Variables

You can set and then use environment variables to facilitate you specification of paths.
To set an environment variable, use set command in the console window. You can set multiple variables.

set path C:\My_Designs\FIFO_8BIT\FIFO_CORE\src
# aldec="C:\Aldec\Active-HDL 8.3"
# ......
# path="C:\My_Designs\FIFO_8BIT\FIFO_CORE\src"
# .....

This way, you can easily handle linked files from multiple sources. For example, you can add files to your design using above defined variables by:

addfile  -vhdl $path\fifo.vhd
# Adding file C:\My_Designs\FIFO_8BIT\FIFO_CORE\src\fifo.vhd ... Done
addfile  -vhdl $path\fifo_tb.vhd
# Adding file C:\My_Designs\FIFO_8BIT\FIFO_CORE\src\fifo_tb.vhd ... Done

Figure 3: Design Browser display of Added Linked Files.

Programs for query ″active hdl 9.3″

Aldec Active-HDL Student Edition


2.7 on 16 votes

Active-HDL Student Edition is a mixed language design entry and simulation tool offered at no cost by Aldec to the students to use during their course work.

ActiveHDL Student Edition … Features of ActiveHDL Student Edition …

HDL Designer


2.5 on 2 votes

HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management …

… deliver a powerful HDL design environment … rulesets
— Interactive HDL visualization and …


IO Checker Verifying hundreds of FPGA IO pins between PCB and FPGA in minutes.

… to the HDL signals that …

HDL Works Ease


4 on 1 vote

HDL Works Ease contains graphical design environment with automated generation of hierarchical VHDL or Verilog code.

HDL Works Ease …



3 on 8 votes

X-HDL 4 is a Verilog VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level …

… directional translator.
X-HDL performs translation … code. X-HDL translates structural …

HDL Sine LUT Generator


3 on 2 votes

This free utility generates HDL Sine Look Up Table Modules in Verilog or VHDL.

… utility generates HDL Sine Look … , and the hdl type and …

ModelSim-Altera Edition


3.1 on 7 votes

ModelSim-Altera Edition software is licensed to support designs written in 100 percent VHDL and 100 percent Verilog …

… as mixed HDL.
Mixed HDL support … behavioral simulation, HDL testbenches, and …



3.1 on 12 votes

The MAX+PLUS II BASELINE software includes support for selected FLEX, ACEX and MAX devices.

… or Verilog HDL you can … and Verilog HDL synthesis, delivers …

Xilinx ISE


3.5 on 186 votes

ISE WebPACK design software is the industry´s only FREE, fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows Vista.

… design offering HDL synthesis and …

Waveform Viewer

Active-HDL offers two waveform viewers:

  • Accelerated Waveform Viewer presenting simulation data stored in the binary simulation database (*.asdb).

  • Standard Waveform Viewer/Editor displaying simulation results saved in the *.awf text file.

By default, the Accelerated Waveform Viewer is enabled and an *.asdb simulation database is created upon initialization of simulation. The Accelerated Waveform Viewer should be the pseered choice for designers working with large amounts of simulation data. It is optimized for large designs and long simulation runs.

The Standard Waveform Viewer/Editor is better suited for working with small designs, especially in the interactive mode. For example, it can show how the current simulation overwrites results from the previous simulation run and allows you to use hotkey stimulators.

Opening a new waveform file and adding signals

  • In order to open a new waveform window, go to New | Waveform from the File menu; click New Waveform on the toolbar.

  • Before you start any simulation you must select signals that represent the input and output ports of the tested model or internal signals. To add signals to the waveform file go to the Design Browser and on the Structure tab, click on the top level design file. Right-clicking on the top level design select Add to Waveform option. This option adds one or more selected objects to the waveform window (in order they are displayed in the Design Browser, order of selection, or order resulting from both manual object multi-selection and then adding the selected signals). You can also add all signals from the selected hierarchy and its sub regions by using the Add to Waveform Recursively option available in the context menu of the Structure tab. You can also add the signals by dragging objects from the upper or lower pane of the Structure tab to the waveform window (see Figure 13).

Figure 13 Adding Signals to Waveform Viewer

Saving the waveform file for off-line viewing

  • When the simulation is finished or has run for the given time, you can save the waveform using File | Save menu.

  • You can open saved .awc file for off-line viewing.

NOTE: Please stop the simulation before saving the waveform file.

Use the restart button to reinitialize the simulation without losing the signals in the waveform.

Saving the waveform file for reuse in successive simulations

The Waveform | Save to macro menu option or the File | Export menu command allow generating a macro (.do file) that can restore the view of the Waveform Viewer in your successive simulation runs and it contains a number of add wave or list commands for each signal found in the *.asdb file (see Figure 14).

Figure 14 Save to Macro

Running a macro file

Saved macro file can be used later to add the signals on the waveform for another simulation run. You can execute this macro in your script immediately after you initialize your simulation.

Creating Workspace and Design

In Active-HDL, individual designs along with their resources (source files, output files with simulation results, etc) can be grouped together as a workspace. The workspace allows adding and working with several designs simultaneously

  • Go to menu File | New and click Workspace. The New Workspace Wizard starts.

  • Type the workspace name and select the location where you want to create the project (you can use the Browse button to locate the folder).

    NOTE: If you check the Create new design option, the New Workspace Wizard will be followed by the New Design Wizard. This way you can create a new workspace and a new design (attached to the workspace) in the same time.

  • Click the OK button when you are done (see Figure 1).

    Figure 1 Create new workspace Wizard (Workspace Window)

  • A window will pop up for creating new design (see Figure 2).

    Figure 2 Create new workspace Wizard (Design Window)

  • Choose the Design Language i.e. Block Diagram Configuration and Default HDL Language (in our case VHDL). Then specify the Target Technology if you have any e.g. Vendor and Technology.

  • Specify the design name and select the location of design folder (exact same as the workspace). The name of the default working library of the design is same as the design name (see figure 3).

    Figure 3 New Design Wizard

  • Click the FINISH button when you are done.

  • The Design Browser now shows a workspace name and new design attached with it (see Figure 4).

    Figure 4 Design Browser after creation of workspace and design

Compiling simulation libraries

You can either use the compile_simlib command or the Compile Simulation Libraries
wizard that simplifies compiling simulation libraries. With these tools, you can
compile all IP core libraries included in the Vivado IP Catalog and the following basic
Xilinx Vivado simulation libraries:




  • SIMPRIM (Verilog Only)

  • SECUREIP (Verilog Only)


  • XPM

You can find detailed description of these libraries in the following document:

Using the Compile Simulation Libraries Wizard

  1. Open Vivado.

  2. Go to Tools | Compile Simulation Libraries.

    Figure 1: Accessing the Compile Simulation Libraries.

  3. The Compile Simulation Libraries will open.

  4. Select Active-HDL under Simulator. Select the desired language and libraries.

    Figure 2: Compile Simulation Libraries: Simulator, Language and Library selection.

  5. Under the Compiled Library Location, select the directory where you want
    the compiled libraries to be saved. Under the Simulator Executable Path,
    provide the path to the directory containing the avhdl.exe file in the
    Active-HDL installation directory.

    Figure 3: Compile Simulation Libraries: Compiled library location and Simulator
    executable path.

  6. By default, all the IP modules available in the Vivado IP Catalog are selected for compilation.
    You can change that behavior by clearing the Compile Xilinx IP check box.
    When cleared, only the basic simulation libraries are compiled. You may also want to enable
    recompilation of libraries already present in the output directory.
    To do so, select the Overwrite the current pre-compiled libraries check box.

    Figure 4: Compile Simulation Libraries: Compile Xilinx IP and Overwrite the current
    pre-compiled libraries.

  7. When you have specified all of your settings, select Compile.

    Figure 5: Compile Simulation Libraries: Compile.

  8. Once the compilation is completed, you should see the compilation summary
    in the Tcl Console similar to the one in the picture below:

    Figure 6: Tcl Console: Compilation Summary.

Using the compile_simlib command

  1. In Vivado Design Suite, execute the following command from the Tcl Console:

    compile_simlib -simulator activehdl -simulator_exec_path <Active-HDL installation folder> -family all -language all -library all -dir <output_folder>



    Specifies a path to the directory where you want compiled libraries to be saved.

    <Active-HDL installation folder>

    Specifies a path to the folder inside Active-HDL installation folder.

    NOTE: It might be required to put the path to the Active-HDL executable in quotes or curly
    brackets as the compile_simlib command does not accept spaces within a path.

    For example, the command may look as follows:

    compile_simlib -simulator activehdl -simulator_exec_path {C:/Aldec/Active-HDL 11.1/BIN} -family all -language all -library all -dir {C:/Aldec/Xilinx_Lib}

    Figure 7: Executing compile_simlib command from the Vivado Tcl Console.

    The above command will compile all simulation and IP libraries written in both languages
    (VHDL and Verilog) for all devices available in Vivado. To disable compilation of IP Core
    libraries and compile only Xilinx simulation libraries, invoke the compile_simlib command
    with the -no_ip_compile argument. You may also want to disable recompilation of libraries
    already present in the output directory by issuing the -force argument.
    To obtain the complete list of available arguments, type compile_simlib -help
    in the Vivado Tcl Console.

  2. Once the compilation is completed, you should see the compilation summary
    in the Tcl Console similar to the one in the picture below:

    Figure 8: Library Compilation Summary.

    The output directory (specified with the -dir argument) will contain
    the configuration file and the folders with pre-compiled libraries.

Оцените статью
Рейтинг автора
Материал подготовил
Андрей Измаилов
Наш эксперт
Написано статей
Добавить комментарий